Dual stress capping layer enhancement study for hybrid orientation finFET CMOS technology

Author

Shin, Kyoungsub ; Chui, Chi On ; King, Tsu-Jae

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

988

Lastpage

991

Abstract

3D stress in FinFET and tri-gate FET structures induced by a tensile or compressive capping layer is studied via simulation. The classic bulk-Si piezoresistance model is then used to predict the impact on carrier mobilities. A tensile capping layer is expected to provide dramatic enhancements (>100%) in electron mobility for a (100)-sidewall fin with lang100rang current flow, while a compressive capping layer is expected to provide modest enhancement (<25%) in hole mobility for a (110)-sidewall fin with lang110rang current flow. Mobility enhancement will be greater for fins with higher aspect ratio, so that a stressed capping layer is expected to be more effective for enhancing FinFET performance

Keywords

CMOS integrated circuits; MOSFET; hole mobility; 3D stress; CMOS technology; FinFET; aspect ratio; bulk-Si piezoresistance; compressive capping layer; dual stress capping layer enhancement; electron mobility; hole mobility; hybrid orientation; sidewall fin; tensile capping; tri gate FET structures; CMOS technology; Compressive stress; Electron mobility; FETs; FinFETs; MOS devices; MOSFETs; Piezoresistance; Silicon on insulator technology; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609528

Filename

1609528