BIR-breaking down the barriers [building in reliability methodology for CMOS wafer fab]

A Building In Reliability (BIR) methodology was incorporated into the development of a sub-micron, double-poly double-metal (DPDM) CMOS wafer fabrication process. This new and proactive approach ensured a reliable process. A multi disciplined team effort was required to understand, control, and measure the critical process parameters which affect the process reliability and manufacturability. Wear out mechanisms of gate oxide integrity, hot electron induced MOSFET degradation, and electromigration were tested on individual process modules to ensure reliability. The benefits from using the BIR methodology are reduced qualification costs, earlier time to market, and greater confidence in process reliability