Detection of trap generation in high-k gate stacks

Author

Young, C.D. ; Heh, D. ; Nadkarni, S. ; Choi, R. ; Peterson, J.J. ; Harris, H.R. ; Sim, J.H. ; Krishnan, S.A. ; Barnett, J. ; Vogel, E. ; Lee, B.H. ; Zeitzoff, P. ; Brown, G.A. ; Bersuker, G.

Author_Institution

SEMATECH, Austin, TX

fYear

2005

fDate

17-20 Oct. 2005

Abstract

Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO₂/HfO₂/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate stacks occurs primarily within the interfacial SiO₂ layer (IL) on the as-grown "precursor" defects most likely caused by the overlaying HfO₂ layer. These results point to the IL as a major focus for reliability improvement of high-k stacks

Keywords

dielectric materials; electron traps; hafnium compounds; interface states; reliability; silicon compounds; titanium compounds; SiO₂-HfO₂-TiN; SiO₂/HfO₂/TiN stacks; charge pumping measurements; constant voltage stress; depth profiling; electron traps; high-k gate stacks; interfacial layer; reliability improvement; threshold voltage instability; trap generation detection; voltage stress-induced generation; Charge measurement; Charge pumps; Current measurement; Electron traps; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Stress measurement; Threshold voltage; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2005 IEEE International

Conference_Location

S. Lake Tahoe, CA

Print_ISBN

0-7803-8992-1

Type

conf

DOI

10.1109/IRWS.2005.1609568

Filename

1609568