SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters

Author

Van Den Bosch, A. ; Steyaert, M. ; Sansen, W.

Author_Institution

ESAT, Katholieke Univ., Leuven, Heverlee, Belgium

Volume

3

fYear

1999

fDate

1999

Firstpage

1193

Abstract

Although very high update rates are achieved in recent publications on high resolution D/A converters, the bottleneck in the design is to achieve a high spurious free output signal bandwidth. The influence of the dynamic output impedance on the chip performance has been analyzed and has been identified as an important limitation for the spurious free dynamic range (SFDR) of high resolution DAC´s. Based on the presented analysis an optimized topology is proposed

Keywords

CMOS integrated circuits; circuit optimisation; digital-analogue conversion; electric impedance; frequency-domain analysis; integrated circuit design; network topology; SFDR-bandwidth limitations; chip performance; current steering CMOS D/A convertors; design; dynamic output impedance; high resolution DAC; high speed convertor; optimized topology; output signal bandwidth; spurious free dynamic range; Bandwidth; CMOS technology; Impedance; Performance analysis; Signal design; Signal resolution; Switches; Switching circuits; Topology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.814383

Filename

814383