Impact of device scaling on deep sub-micron transistor reliability - a study of reliability trends using SRAM

Author

White, Mark ; Huang, Bing ; Qin, Jin ; Gur, Zvi ; Talmor, Michael ; Chen, Yuan ; Heidecker, Jason ; Nguyen, Duc ; Bernstein, Joseph

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA

fYear

2005

fDate

17-20 Oct. 2005

Abstract

As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today´s high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr´s qualification data

Keywords

CMOS integrated circuits; SRAM chips; embedded systems; integrated circuit modelling; integrated circuit reliability; 0.13 micron; 0.15 micron; 0.25 micron; CMOS technology; SRAM; current acceleration models; deep sub-micron transistor reliability; device scaling; high-reliability aerospace applications; high-reliability space applications; step-stress techniques; temperature life-stress relationship; voltage life-stress relationship; Acceleration; CMOS technology; Industrial relations; Microelectronics; Random access memory; Semiconductor device modeling; Space technology; Temperature; Transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2005 IEEE International

Conference_Location

S. Lake Tahoe, CA

Print_ISBN

0-7803-8992-1

Type

conf

DOI

10.1109/IRWS.2005.1609574

Filename

1609574