Matching variation after HCI stress in advanced CMOS technology for analog applications

In this report, hot carrier stress impact on mismatch properties of n and p MOS transistors with different sizes produced using 0.15 μm CMOS technology is presented for the first time. The research reveals that HCI does degrade matching of nMOSFETs´ properties, but, for pMOSFETs, the changes are minor. Due to matching variation after HCI stress, for analog circuits´ parameters, it is found that the after stress lines of n and pMOSFETs exhibit cross points for both σ (□ V_t,op) and σ (□I_ds,op/I_ds,op) drawings. It is suggested that the cross points can be used to indicate the minimal size for n and p pairs to have the same degree of mismatch in designing analog circuits. In addition, the interpretations for the differences in n to pMOSFETs and I_ds,op to I_ds,sat mismatches are provided with experimental verifications.