A chip design and implementation of a 13-bit high-order oversampling modulator for ISDN-U interface

Author

Wu, S.-M. ; Liu, R.-Y. ; Chu, Y.-C.

Author_Institution

Dept. of Electr. Eng., Yuan Ze Univ., Tao-Yuan, Taiwan

Volume

3

fYear

1999

fDate

1999

Firstpage

1381

Abstract

In this paper, presented is a chip design and implementation of a 13-bit, 4th-order with single-bit output oversampling modulator. The signal bandwidth is 80 kHz and the specification meets the ISDN-U interface. An overload detector circuit is designed in VHDL to solve the inherent instability problem in the high-order oversampling modulator. The noise problems and the techniques to improve them are also discussed. While the OSR is 64, the resulting design operates at 10.24 MHz. The SNR is 75.83 dB, the power supply is ±2.5 V, the power consumption is 48.63 mW, and the die area is 1800 μm×1800 μm fabricated in a 0.5 μm CMOS 2P2M process

Keywords

CMOS integrated circuits; ISDN; integrated circuit design; integrated circuit noise; mixed analogue-digital integrated circuits; modulators; sigma-delta modulation; signal sampling; telecommunication equipment; -2.5 V; 0.5 micron; 10.24 MHz; 13 bit; 2.5 V; 48.63 mW; 75.83 dB; ADC; CMOS 2P2M process; ISDN-U interface; VHDL; chip design; high-order oversampling modulator; noise problems; overload detector circuit; single-bit output; Bandwidth; Chip scale packaging; Circuits; Detectors; Negative feedback; Operational amplifiers; Passive filters; Signal synthesis; Signal to noise ratio; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.814427

Filename

814427