Title :
Inductance effect for interconnection timing analysis in submicronic circuits
Author :
Servel, G. ; Kenmei, B. ; Huret, F. ; Paleczny, E. ; Kennis, P. ; Deschacht, D.
Author_Institution :
Lab. d´´Inf., de Robotique et de Microelectron., CNRS, Montpellier, France
Abstract :
The object of this paper is to verify if the RC distributed model is always sufficient to characterize the propagation delay and the degradation due to the interconnect lines in sub-micronic process by comparing the simulation results obtained by electrical simulations to an electromagnetic approach for a large range of interconnection length, input slope and geometries. Limits between RC and RLC models are determined
Keywords :
VLSI; circuit simulation; delays; inductance; integrated circuit interconnections; integrated circuit modelling; timing; RC distributed model; RLC models; electrical simulations; geometries; inductance effect; input slope; interconnect lines; interconnection length; interconnection timing analysis; propagation delay; submicronic circuits; Circuit analysis; Electromagnetic propagation; Frequency; Inductance; Integrated circuit interconnections; Integrated circuit modeling; Propagation delay; Semiconductor device modeling; Solid modeling; Timing;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.814432
