Accelerated logic simulation using parallel processing

Author

Hoppe, Friedrich

Author_Institution

Inst. fur Tech. Inf., Berlin, West Germany

fYear

1988

fDate

11-14 Apr 1988

Firstpage

156

Lastpage

163

Abstract

The author presents a modified time-warp algorithm for parallel logic simulation using circuit partitioning. The algorithm allows a processor to roll back its simulation time to any given point in the past, only using the input queue. The memory space for the state queue and the output queue and the computing effort to handle them can be saved. A software model of a distributed system has been developed as test environment for the implementation of the modified algorithm, which is compared with the link time algorithm and with a sequential simulation. It is shown that the speedup of the time-warp method is less dependent on cycles in the communication graph (feedbacks in the test-circuit) than the link time method

Keywords

circuit analysis computing; logic CAD; parallel processing; accelerated logic simulation; circuit partitioning; communication graph; distributed system; feedbacks; input queue; link time algorithm; memory space; output queue; parallel logic simulation; parallel processing; sequential simulation; software model; state queue; test environment; test-circuit; time-warp algorithm; Acceleration; Circuit simulation; Computational modeling; Logic circuits; Parallel processing; Partitioning algorithms; Software algorithms; Software testing; System testing; Time warp simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '88. 'Design: Concepts, Methods and Tools'

Conference_Location

Brussels

Print_ISBN

0-8186-0834-X

Type

conf

DOI

10.1109/CMPEUR.1988.4948

Filename

4948