DocumentCode
3448246
Title
Design of Totally Self-Checking Sequential Circuits
Author
Greblicki, Jerzy W. ; Kotowski, Jerzy
Author_Institution
Control & Robot., Wroclaw Univ. of Technol., Wroclaw, Poland
fYear
2009
fDate
10-12 Sept. 2009
Firstpage
1
Lastpage
6
Abstract
Methods of designing of totally self checking sequential machines are presented in this paper. The main problem in TSC sequential machines (TSC SM) designing is synthesis TSC functional excitation circuit. Formal condition of self testing (ST) property for AND-OR structures are given. New method of circuit minimization is presented and ST of minimized circuits is proofed. We also present a methodology of designing of TSC SM. Owing to our methods we can design TSC circuits in a fully automatic way.
Keywords
VLSI; automatic testing; circuit optimisation; logic design; sequential circuits; sequential machines; AND-OR structures; circuit minimization; sequential circuits; totally self checking sequential machines; Aerospace safety; Automatic testing; Built-in self-test; Circuit faults; Circuit synthesis; Design methodology; Electrical fault detection; Fault detection; Samarium; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Logistics and Industrial Informatics, 2009. LINDI 2009. 2nd International
Conference_Location
Linz
Print_ISBN
978-1-4244-3958-4
Electronic_ISBN
978-1-4244-3958-4
Type
conf
DOI
10.1109/LINDI.2009.5258681
Filename
5258681
Link To Document