Delay-power performance analysis

Author

Cremoux, S. ; Aline, M. ; Azemard, N. ; Auvergne, D.

Author_Institution

Lab. d´´Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France

Volume

3

fYear

1999

fDate

1999

Firstpage

1543

Abstract

Based on an incremental path search algorithm, this paper addresses the problem of low power performance driven path classification by sizing selected gates on the shortest and the longest identified paths of the circuit. Delay and power/area constraints are managed using circuit path sizing alternatives defined through a realistic evaluation of gate power and delay. Demonstration of this technique is given on examples of path enumeration and optimization evaluated on several ISCAS´85 benchmarks. Implemented in the POPS tool (Performance Optimization by Path Selection), the accuracy of this technique is compared to evaluation obtained from the EPIC tool with SPICE used as a reference

Keywords

circuit CAD; circuit optimisation; delay estimation; digital integrated circuits; integrated circuit design; low-power electronics; search problems; POPS tool; delay constraints; delay-power performance analysis; gate delay; gate power; gates sizing; incremental path search algorithm; low power design; low power performance driven path classification; path enumeration; path optimization; power/area constraints; transistor sizing; Circuits; Delay effects; Delay estimation; Electronic mail; Energy management; Optimization; Performance analysis; Robots; SPICE; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.814465

Filename

814465