Towards an MPEG-4 HW/SW integrated solution: an efficient SIMD architecture for exhaustive BMA

Author

Sayed, Mohammed ; Badawy, Wael

Author_Institution

Dept. of Electr. & Comput. Eng., Calgary Univ., Alta.

fYear

2005

fDate

5-6 Dec. 2005

Firstpage

495

Lastpage

503

Abstract

This paper presents an efficient SIMD architecture for exhaustive block matching algorithm (EBMA). This module is part of the MPEG-4 part 9: reference hardware description. The developed module is prototyped and synthesized for Xilinx Virtex II FPGA XC2V3000-4. The proposed module processes 30.75 CIF frame /sec using the max clock frequency. This module utilizes 12% of the register bits, 16% of the block RAMs, and 15% of the LUTs in Xilinx Virtex II FPGA XC2V3000-4

Keywords

field programmable gate arrays; hardware description languages; parallel processing; video signal processing; MPEG-4 HW/SW integrated solution; SIMD architecture; Xilinx Virtex II FPGA XC2V3000-4; exhaustive block matching algorithm; max clock frequency; reference hardware description; Computational efficiency; Computer architecture; Field programmable gate arrays; Handheld computers; Hardware; MPEG 4 Standard; Motion estimation; Prototypes; Video coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Information and Communications Technology, 2005. Enabling Technologies for the New Knowledge Society: ITI 3rd International Conference on

Conference_Location

Cairo

Print_ISBN

0-7803-9270-1

Type

conf

DOI

10.1109/ITICT.2005.1609646

Filename

1609646

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3448646