Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator

Author

Kuo, J.B. ; Chen, Y.W.

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1991

fDate

9-10 Sep 1991

Firstpage

97

Lastpage

100

Abstract

The authors present a device-level study on the transient behavior of a 1-μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3-D device simulator, derived from PISCES-2B, in which layout information on each transistor and an efficient large-scale simulation capability have been added. According to simulation results, the speed performance of the BiCMOS inverter is determined by the charge transport in the base of the pull-up bipolar device, which is controlled by the circuit operating conditions set by the associated NMOS and PMOS devices

Keywords

BIMOS integrated circuits; circuit analysis computing; integrated logic circuits; transient response; 1 micron; BiCMOS inverter circuit; PISCES-2B; charge transport; device-level study; large-scale simulation capability; layout information; pull-up bipolar device; quasi-3D device simulator; six-transistor configuration; transient analysis; Analytical models; BiCMOS integrated circuits; Circuit optimization; Circuit simulation; Inverters; Large-scale systems; MOS devices; Performance analysis; Transient analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1991., Proceedings of the 1991

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-0103-X

Type

conf

DOI

10.1109/BIPOL.1991.160965

Filename

160965