Genetic partitioning and placement for VLSI circuits

Author

Sipakoulis, G.C. ; Karafyllidis, Ioannis ; Thanailakis, Adonios

Author_Institution

Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece

Volume

3

fYear

1999

fDate

1999

Firstpage

1647

Abstract

An adaptive genetic algorithm for VLSI circuit partitioning and another for VLSI circuit placement are presented in this paper. These genetic algorithms are able to modify some of their own parameters during the search, based on their performance. These parameters are: population size, crossover rate and mutation rate. The algorithms are applied to partitioning and placement of a circuit, respectively, and their performance is compared with the performance of a non-adaptive genetic algorithm. The proposed genetic algorithms lead to significantly superior solutions in less computation time

Keywords

VLSI; circuit layout CAD; genetic algorithms; integrated circuit layout; network routing; VLSI circuits; circuit partitioning; computation time; crossover rate; genetic partitioning; mutation rate; placement; population size; Circuits; Computer aided analysis; Genetic algorithms; Genetic mutations; Joining processes; Laboratories; Materials science and technology; Partitioning algorithms; Routing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.814490

Filename

814490