Title :
Fault secure binary counter design
Author :
Karaolis, E. ; Nikolaidis, S. ; Goutis, C.E.
Author_Institution :
Dept. of Phys., Aristotelian Univ. of Thessaloniki, Greece
Abstract :
An architecture for fault secure synchronous binary counters is introduced in this paper. It is based on the parity prediction technique. At each counter state the parity of the counter outputs of the following state is predicted and with the next clock pulse it is compared to the current one. A full analysis of the effect of errors provoked by possible single faults on the circuit elements and interconnections proves the validity of the fault secure property in the proposed architecture
Keywords :
circuit reliability; counting circuits; errors; logic circuits; logic design; errors; fault secure binary counter design; parity prediction technique; single faults; synchronous binary counters; Built-in self-test; Circuit faults; Counting circuits; Digital systems; Electrical fault detection; Equations; Fault detection; Logic; Physics computing; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.814493
