Title :
A global optimization tool for CMOS logic circuits
Author :
Delaurenti, M. ; Graziano, M. ; Masera, G. ; Piccinini, G. ; Zamboni, M.
Author_Institution :
Dipt. di Elettronica, Politecnico di Torino, Italy
Abstract :
Transistor sizing has been proved to be a very efficient technique for improving the performance of CMOS logic circuits in terms of both speed and power consumption. In this paper, new simple and accurate delay and power models are proposed: these models are integrated with time efficient algorithms for the transistor size optimization of large, generic CMOS circuits. Additionally the developed tool includes models for the noise evaluation: as one of the effects of noise in high performance circuits is the increasing of the delay along critical paths, the adopted noise model has been integrated in the delay equations, with the aim of improving the quality of the performed optimization
Keywords :
CMOS logic circuits; circuit CAD; circuit layout CAD; circuit optimisation; delay estimation; high level synthesis; integrated circuit noise; CMOS logic circuits; delay equations; delay model; global optimization tool; high performance circuits; noise evaluation; noise model; power model; transistor size optimization; transistor sizing; CMOS logic circuits; Central Processing Unit; Circuit noise; Constraint optimization; Delay effects; Delay estimation; Energy consumption; Optimization methods; Power dissipation; Semiconductor device modeling;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.814496
