Design of a Reusable IP Core; Timing Generator for Synchronous Digital Hierarchy Systems

Author

Aliabadi, Maryam Raiyat ; Zadeh, Ahmad Khadem

Author_Institution

IRAN Telecom Res. Center, Tehran

fYear

2005

fDate

5-6 Dec. 2005

Firstpage

929

Lastpage

934

Abstract

The availability of reusable IP-cores, increasing time to market and design productivity gap, and enabling deep sub-micron technologies have led to core-based system-on-chip (SoC) design as a new paradigm in electronic system design especially in more applicable embedded systems. For this purpose, we have designed a well-verified and synthesizable IP named: "timing generator for synchronous transport module (STM-I) frame" for synchronous digital hierarchy systems base on ITU-T G707 and virtual socket interface alliance (VSIA) standards. The top level of this IP has been designed and verified in the HDS environment of cadence tools and it has been synthesized by design compiler, synopsis synthesis tool

Keywords

embedded systems; logic design; synchronous digital hierarchy; system-on-chip; ITU-T G707; embedded systems; reusable IP core; synchronous digital hierarchy systems; synchronous transport module frame; system-on-chip design; timing generator; virtual socket interface alliance standards; Design optimization; Embedded system; Process design; Productivity; Synchronous digital hierarchy; Synchronous generators; System-on-a-chip; Telecommunications; Time to market; Timing; Synchronous Digital Hierarchy Intellectual Property; Synthesizable; Timing Generator; Well-verified;

fLanguage

English

Publisher

ieee

Conference_Titel

Information and Communications Technology, 2005. Enabling Technologies for the New Knowledge Society: ITI 3rd International Conference on

Conference_Location

Cairo

Print_ISBN

0-7803-9270-1

Type

conf

DOI

10.1109/ITICT.2005.1609677

Filename

1609677