• DocumentCode
    3449560
  • Title

    Generalization of parallel analysis for a power electronic system by circuit partitioning

  • Author

    Kato, Toshihiko ; Inoue, Ken ; Kotani, Yoshinori ; Ogawa, Tomomi

  • Author_Institution
    Dept. of Electr. Eng., Doshisha Univ., Kyotanabe, Japan
  • fYear
    2013
  • fDate
    23-26 June 2013
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    This paper proposes a general-purpose numerical technique of a new fast parallel circuit simulation method for a power electric system by applying an explicit integration formula to selected energy storage elements such as inductors and/or capacitors. The optimum step-size is selected for each subcircuit. A general parallel method is proposed to utilize thread processing techniques based on the OpenMP application program interfaces with a multicore CPU and shared-memory system to reduce its processing time. Its efficiency is validated by the effects of reducing numbers of time steps and circuit sizes of example circuits.
  • Keywords
    application program interfaces; electronic engineering computing; multi-threading; multiprocessing systems; power electronics; shared memory systems; OpenMP application program interfaces; capacitors; circuit partitioning; circuit sizes; energy storage elements; explicit integration formula; fast parallel circuit simulation method; general-purpose numerical technique; inductors; muiticore CPU; optimum step-size; power electric system; power electronic system; shared-memory system; thread processing techniques; time steps; Instruction sets; Process control; Size control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Control and Modeling for Power Electronics (COMPEL), 2013 IEEE 14th Workshop on
  • Conference_Location
    Salt Lake City, UT
  • ISSN
    1093-5142
  • Print_ISBN
    978-1-4673-4914-7
  • Type

    conf

  • DOI
    10.1109/COMPEL.2013.6626442
  • Filename
    6626442