Title :
Energy and performance models for clocked and asynchronous communication
Author :
Stevens, Kenneth S.
Author_Institution :
Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
Parameterized first-order models for throughput, energy, and bandwidth are presented in this paper. Models are developed for many common pipeline methodologies, including clocked flopped, clocked time-borrowing latch protocols, asynchronous two-cycle, four-cycle, delay-insensitive, and source synchronous. The paper focuses on communication costs which have the potential to throttle design performance as scaling continues. The models can also be applied to logic. The equations share common parameters to allow apples-to-apples comparisons against different design targets and pipeline methodologies. By applying the parameters to various design targets, one can determine when unclocked communication is superior at the physical level to clocked communication in terms of energy for a given bandwidth. Comparisons between protocols at fixed targets also allow designers to understand tradeoffs between implementations that have a varying degree of timing assumptions and design requirements.
Keywords :
asynchronous sequential logic; delays; integrated circuit modelling; logic CAD; pipeline processing; timing; apples-to-apples comparisons; asynchronous communication; asynchronous two-cycle; bandwidth; clocked communication; clocked flopped; clocked time-borrowing latch protocols; delay-insensitive; design requirements; design targets; energy; four-cycle; parameterized first-order models; performance models; pipeline methodologies; source synchronous; throughput; timing assumptions; unclocked communication; Asynchronous communication; Bandwidth; Clocks; Costs; Delay; Differential equations; Logic; Pipelines; Protocols; Throughput;
Conference_Titel :
Asynchronous Circuits and Systems, 2003. Proceedings. Ninth International Symposium on
Print_ISBN :
0-7695-1898-2
DOI :
10.1109/ASYNC.2003.1199166