Sub-15 ps gate delay with new AC-coupled active pull-down ECL circuit

Author

Toh, Kai-yap ; Warnock, James D. ; Cressler, John D. ; Jenkins, Keith A. ; Danner, David A. ; Chen, Tze-Chiang

Author_Institution

IBM, Yorktown Heights, NY, USA

fYear

1991

fDate

9-10 Sep 1991

Firstpage

136

Lastpage

138

Abstract

An ECL (emitter coupled logic) circuit with an AC-coupled active pull-down emitter follower configuration is described. An unloaded ring oscillator gate delay of 13.2 ps has been achieved at 6.2 mW, in a 50 GHz-f_T ion-implanted silicon bipolar technology. This circuit could be useful as an internal gate operating at low-power and as an I/O gate to drive a large capacitive load at high-power. In both cases, this circuit offers superior power-delay performance compared to conventional ECL circuits

Keywords

bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; oscillators; 13.2 ps; 50 GHz; 6.2 mW; AC-coupled active pull-down; ECL circuit; I/O gate; Si; bipolar technology; emitter coupled logic; emitter follower; gate delay; high-speed digital circuits; internal gate; ion implantation; large capacitive load; power-delay performance; ring oscillator; Circuits; Delay; Energy consumption; Power dissipation; Power supplies; Radio frequency; Resistors; Ring oscillators; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1991., Proceedings of the 1991

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-0103-X

Type

conf

DOI

10.1109/BIPOL.1991.160971

Filename

160971