Efficient parallel searching with TCAMs

Chip-level parallel TCAMs were deployed to circumvent the limitation of a single TCAM. In this paper, we propose a crossed address range division and integral caching scheme. We improve the update efficiency significantly by buddy update method while keep low power dissipation by decreasing the number of the triggered TCAMs access in each lookup operation. The lookup throughput is ultra high through adaptive load balance. Our simulation results show that the proposed scheme can achieve an average lookup speedup factor greater than 11 with 12 TCAM chips, given 10% more memory space.