Title :
Testable design of microcontrollers using a RISC approach
Author_Institution :
Dept. of Electron. & Telecommun., Bucharest Univ., Romania
Abstract :
This paper deals with the CPU design for microcontrollers as a RISC architecture using design for testability techniques. The instruction set is defined, the processor logic design is performed and the on chip structure for test vectors generation, using the minimum area, is presented. We used the results of algorithmic information theory to balance the complexity of the self test machine with that of the test sequence, so that the area is minimised
Keywords :
computer architecture; computer testing; design for testability; instruction sets; integrated circuit design; integrated circuit testing; logic design; microcontrollers; reduced instruction set computing; CPU design; RISC architecture; algorithmic information theory; area minimisation; complexity; design for testability; instruction set; microcontrollers; on chip structure; processor logic design; self test machine; test sequence; test vectors generation; Automatic testing; Controllability; Design for testability; Information theory; Logic design; Logic testing; Microcontrollers; Performance evaluation; Pipelines; Reduced instruction set computing;
Conference_Titel :
Semiconductor Conference, 1995. CAS'95 Proceedings., 1995 International
Conference_Location :
Sinaia
Print_ISBN :
0-7803-2647-4
DOI :
10.1109/SMICND.1995.494902
