High voltage trench drain LDMOS-FET using SOI wafer

Author

Baba, Yoshiro ; Yanagiya, Satoshi ; Koshino, Yutaka ; Udo, Yuso

Author_Institution

Micro Electron. Center, Toshiba Corp., Kawasaki, Japan

fYear

1994

fDate

31 May-3 Jun 1994

Firstpage

183

Lastpage

186

Abstract

Silicon direct bonding and deep trench techniques are a good combination for high density and high voltage ICs such as display drivers. High voltage devices in these ICs are perfectly isolated by thick SOI oxide and isolation trenches. The SOI oxide thickness increases the blocking voltage of full depletion devices. On the other hand, it increases the warpage of SOI wafers and makes troubles in handling them. The new trench drain structure solves these problems and provides high voltage, low ON resistance LDMOS-FET. Its drain-source blocking voltage is 290 V, and the ON resistance is 0.37 Ωcm² including the isolation area

Keywords

power MOSFET; 290 V; HV trench drain LDMOS-FET; SOI oxide thickness; SOI wafer; Si; Si direct bonding; deep trench technique; drain-source blocking voltage; full depletion devices; high voltage ICs; isolation trenches; on resistance; thick SOI oxide; Dielectrics; Displays; Driver circuits; FETs; Low voltage; Oxidation; Semiconductor materials; Silicon; Thickness control; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1994. ISPSD '94., Proceedings of the 6th International Symposium on

Conference_Location

Davos

ISSN

1063-6854

Print_ISBN

0-7803-1494-8

Type

conf

DOI

10.1109/ISPSD.1994.583700

Filename

583700