Title :
Highly digitalized Flash analog to digital (FADC) converter using Mux based decoder topology
Author :
Palsodkar, Prasanna ; Dakhole, P. ; Palsodkar, Prasanna ; Kale, Aniket Vilas
Author_Institution :
Dept. of Electron. Eng., Yeshwantrao Chavan Coll. of Eng., Nagpur, India
Abstract :
In this paper Flash ADC (FADC) is Implemented in 0.18 μm technology using CMOS Inverter based Threshold inverter Quantized (TIQ) comparator for effective speed and power improvement by eliminating complete resistive ladder circuit. Thermometer to binary decoder with low power consumption, less area & short critical path is selected for the design of low power high speed FADC. Presence of bubble error reduces output correction capability. An advanced scheme is proposed for correction of bubble error in Mux based decoder. FADC comparators designed with systematic sizing of transistors where linearity measures of convertor include 0.42 LSB INL, +0.62/-0.75 LSB DNL and ENOB 3.09 at 20 MHz.
Keywords :
CMOS logic circuits; analogue-digital conversion; binary codes; comparators (circuits); decoding; ladder networks; logic gates; CMOS inverter; FADC comparators; FADC converter; TIQ comparator; binary decoder; bubble error; frequency 20 MHz; highly digitalized flash analog to digital converter; low power consumption; low power high speed FADC design; mux based decoder topology; resistive ladder circuit; short critical path; size 0.18 mum; thermometer; threshold inverter quantized comparator; transistor systematic sizing; Decoding; Hardware; Inverters; Multiplexing; Power demand; Read only memory; Transistors;
Conference_Titel :
Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN), 2012 1st International Conference on
Conference_Location :
Gujarat
Print_ISBN :
978-1-4673-1628-6
DOI :
10.1109/ET2ECN.2012.6470060
