• DocumentCode
    3450504
  • Title

    Planarization techniques in GaAs processing

  • Author

    Müller, A. ; Rizescu, R. ; Petrini, I. ; Avramescu, V. ; Corici, A. ; Craciunoiu, F.

  • Author_Institution
    ICCE, Bucharest, Romania
  • fYear
    1995
  • fDate
    11-14 Oct 1995
  • Firstpage
    313
  • Lastpage
    316
  • Abstract
    The most important planarization techniques used in GaAs processing are presented. These techniques are necessary because in GaAs FET and MMIC-technology non planar, mesa etched surfaces are present under the resist. There is presented the use of bi and three level planarization techniques in a GaAs NLTL MMIC processing
  • Keywords
    III-V semiconductors; MMIC; gallium arsenide; integrated circuit technology; surface treatment; FET technology; GaAs; NLTL MMIC processing; bilevel planarization; nonplanar mesa etched surfaces; resist; three level planarization; Dielectric films; Dielectric substrates; Etching; FETs; Fabrication; Gallium arsenide; Lithography; Planarization; Resists; Surface topography;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Conference, 1995. CAS'95 Proceedings., 1995 International
  • Conference_Location
    Sinaia
  • Print_ISBN
    0-7803-2647-4
  • Type

    conf

  • DOI
    10.1109/SMICND.1995.494924
  • Filename
    494924
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3450504