Sampled analog VLSI architecture using OP-AMP based switched capacitor circuits to implement discrete Haar wavelet transform

We proposed a sampled analog VLSI architecture to implement discrete Haar wavelet transform (DHWT). Gain-boosted folded cascode operational amplifier based switched capacitor integrator circuit serves as the building block for the proposed architecture. This architecture performs DHWT operation on real-time samples which are discrete in time but continuous in amplitude. This produces DHWT samples without generating intermediate low frequency samples. This architecture gives good economy in the silicon area usage with low design complexity due to the absence of the quantization process and thus of the data converters. Simulation results for this implementation in 0.18µm UMC process are presented.