Reconfiguration mechanism for an IP block based interconnection

This paper presents a reconfiguration mechanism for an on-chip interconnection scheme called Heterogeneous IP Block Interconnection (HIBI). Required memory structures and logical signal operations for the different configurations are explained. The possible applications for this kind of reconfiguration are discussed, including ways to enhance system performance, ease of design re-use, low power designs and fault tolerance. An overview of HIBI is given as a background information for the reader. The HIBI architecture is designed to exploit VHDL synthesis but the concept could conceivably be transferred to any synthesis environment