CA optimization based on simulation annealing in BIST

The deterministic test patterns generator in BIST often suffer from the problems that it requires extra test power consumption, area overhead and the idle test cycles between the test patterns. This paper proposes an efficient strategy for synthesizing a built-in test pattern generator that can generate a given set of predetermined low power test patterns for reducing the test power of a circuit under test (CUT) without modifying the initial fault coverage. The technique is based on the cellular automata (CA) model for testing combinational circuits. The algorithm we present based on simulation annealing (SA) that can optimize a CA structure to generate given low power test sequence by adjusting dynamically cell neighborhood range of CA. The results of simulation using benchmark combinational circuits showed that the designing generator is efficient to generate the deterministic test sequences in terms of power consumption, fault coverage, test time and area overhead compared to alternative solution.