A simulation study of pipelining and decoupling a dynamic instruction scheduling mechanism

As instruction window size increases, it becomes difficult to maintain processor cycle time. Pipelining the instruction window is not a solution for maintaining the processor cycle time, since it is said that it affects processor performance seriously. However, the pipelining has not been evaluated quantitatively. Therefore, in this paper, we evaluate a dynamic instruction scheduling mechanism whose wakeup and select logic is pipelined. On the other hand, recent interests on data speculation demand to further increase the instruction window size in order to realize instruction reissue mechanism which deals with incorrect data speculations. For the purpose of reducing the instruction window size with maintaining the instruction reissue capability, we propose to decoupling the reissue mechanism from the scheduling mechanism. Using a cycle-by-cycle simulator, we have evaluated the pipelining and the decoupling of the instruction window