Two-level logic synthesis on PAL-based CPLD and FPGA using decomposition

The PAL-based structure constitutes the kernel of many CPLD and FPGA devices. The problem of appropriate decomposition of the whole devices under design into suitable parts which can be realized as single PAL-based logic blocks containing the limited number of terms, is one of basic problems of the synthesis process. The method of two-level logic synthesis that makes use of three-state output buffers constituting the additional internal resources of logic blocks, is presented in this paper. Developed algorithms, implemented within the Decomp system, have been used for partitioning the benchmark circuits due to realization by means of the PAL-based logic blocks with the given number of terms. Synthesis of benchmark circuits for standard PAL20V8 devices has also been carried out and the obtained results have been compared to the ones published previously