Learning in hardware: architecture and implementation of an FPGA-based rough set machine

The “Learning Hardware” approach proposed here involves creating a computational network based on feedback from the environment (for instance, positive and negative examples from the trainer), and realizing this network in an array of Field Programmable Gate Arrays (FPGAs). We advocate the approaches based on a “strong AI criterion”; for instance, the computational networks can be built based on Sum-of-Products logic minimization, functional logic decomposition, or Decision Tree construction. Here we propose the constructive induction approach to Learning Hardware based on Rough Sets Theory (RST). This approach allows the use of logical analysis to develop efficient hardware-realizable algorithms, and is contrasted with the popular Evolvable Hardware (EHW) approach in which learning/evolution is based on the genetic algorithm only. The RST algorithms have a natural high parallelism and high possible speed-ups. Using a fast prototyping tool, the DEC-PERLE-1 board based on an array of Xilinx FPGAs, we are developing a virtual SIMD processor that accelerates the learning (design) of optimized multi-valued logic nets