DocumentCode
345138
Title
Application of FHM-based design method to scalable 2-D DCT processor
Author
Shigehara, E. ; Takeuchi, Yoshio ; Imai, Masayoshi ; Kimura, Tsutomu
Author_Institution
Dept. of Inf. & Math. Sci., Osaka Univ., Japan
Volume
1
fYear
1999
fDate
1999
Firstpage
406
Abstract
This paper studies digital signal processor design using Flexible Hardware Model (FHM). The proposed method is based on design reuse and a quantitative estimation of design quality derived from FHM. In this paper, 2-D DCT processor example shows the effectiveness of our proposed approach
Keywords
VLSI; data compression; digital signal processing chips; discrete cosine transforms; image coding; FHM-based design method; design reuse; digital signal processor design; flexible hardware model; quantitative estimation; scalable 2-D DCT processor; Costs; Design methodology; Digital signal processing; Discrete cosine transforms; Hardware; Image coding; Informatics; Productivity; Transform coding; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
EUROMICRO Conference, 1999. Proceedings. 25th
Conference_Location
Milan
ISSN
1089-6503
Print_ISBN
0-7695-0321-7
Type
conf
DOI
10.1109/EURMIC.1999.794501
Filename
794501
Link To Document