Performance Optimization of Flagged BCD Adder

This paper presents a decimal adder which is hardware, speed and power efficient. Conventional BCD addition usually concludes by adding the correction bits to the result, which often proves to consume lot of processing latency, hence instead of adding correction bits appropriate flag bits are generated thus reducing the delay and the hardware encountered decimal correction. Various fast adders like Brent-Kung, Kogge-Stone, Sklansky, Knowles, Ladner Fischer, Han-Carlson have been used to implement this. A comparative study based on the number of LUT´s consumed and the combinational delay encountered in the critical path for different adders is performed for various device families. Verilog code has been used to design the proposed BCD adder and it is simulated using ISim. A delay improvement of 9.03% is achieved by the architecture of the BCD adder proposed in this paper.