Development of the CRC block for Zigbee Standard on FPGA

Author

Ahmad, Rafidah ; Sidek, Othman ; Mohd, Shukri Korakkottil Kunhi

Author_Institution

Collaborative Microelectron. Design Excellence Centre (CEDEC), Univ. Sains Malaysia, Nibong Tebal, Malaysia

fYear

2009

fDate

14-15 Dec. 2009

Firstpage

1

Lastpage

4

Abstract

CRC (cyclic redundancy check) block was developed on FPGA (field programmable gate array) in order to meet the needs for simple, low-power and low-cost wireless communication such as Zigbee. Zigbee operates primarily in the 2.4 GHz band, which makes the technology easily applicable and worldwide available. This paper gives a short overview of CRC block in the digital transmitter based on Zigbee standard. The purpose of the research is to diversify the design methods by using the Verilog code entry through Xilinx ISE 8.2i. Here, the simulation and measurement results are also presented to verify the functionality of the CRC block. The data rate of CRC block is 250 kbps.

Keywords

cyclic redundancy check codes; field programmable gate arrays; hardware description languages; personal area networks; radio transmitters; CRC block; FPGA; Verilog code; Xilinx ISE 8.2i; Zigbee standard; bandwidth 2.4 GHz; cyclic redundancy check block; digital transmitter; field programmable gate array; wireless communication; Batteries; Cyclic redundancy check; Design methodology; Field programmable gate arrays; Hardware design languages; Physical layer; Standards development; Transmitters; Wireless communication; ZigBee; CRC; FPGA; Verilog; Xilinx; Zigbee;

fLanguage

English

Publisher

ieee

Conference_Titel

Technical Postgraduates (TECHPOS), 2009 International Conference for

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4244-5223-1

Electronic_ISBN

978-1-4244-5224-8

Type

conf

DOI

10.1109/TECHPOS.2009.5412047

Filename

5412047