Design of Image Data Compression IP Core Based on Processor Local Bus

The system on a programmable chip (SoPC) based on FPGA has some special characteristics, such as flexibility, customization, programmable hardware and software. The design of user intellectual property (IP) core is an important task in the design of SoPC. This paper presents the design of image data compression IP core based on the standard of processor local bus (PLB). The IP core is based on CCSDS image data compression (IDC) standard which includes discrete wavelet transform module and bit plane encoder module. Furthermore, the interface between PLB and IDC IP core is also designed. The design program of each module is using the language of VHDL, simulated by the software modelsim, and realized by the software EDK. The IP core designed in the SoPC system greatly speeds the encoding and makes the design easier and stronger in expansibility.