A 150 V, 320 MHz, low noise self-aligned double diffused lateral (SADDL) pnp transistor

For realization of complementary transistors needed in high voltage, high speed analog ICs, high voltage, high performances lateral pnp transistors have been developed by utilizing the SADDL transistor structure. The developed lateral pnp transistor has a high h_FE of l00, high f_T of 320 MHz and low noise figure of 3 dB in spite of a high BV_CEO of 150 V. When BV_CEO of the developed SADDL transistor is 340 V, h_FE is 50 and f_T is 120 MHz. These f_T´s are about 5 times those of the best conventional lateral pnp transistors with the same BV_CEO, as reported to date