A 7GHz 1mV-input-resolution comparator with 40mV-input-referred-offset compensation capability in 65NM CMOS

Author

Huynh, A.T. ; Ta, Chien M. ; Nadagouda, Praveen ; Evans, Robin J. ; Skafidas, E.

Author_Institution

Dept. of Electr. & Electron. Eng., Univ. of Melbourne, Melbourne, VIC, Australia

fYear

2011

fDate

8-11 May 2011

Abstract

A 7GHz-clock 1mV-input-resolution comparator is designed and simulated in a 65nm CMOS process. The comparator off-set is compensated by changing the body voltages of the input differential triple-well NFET transistor pair. A reset switch is added between two regeneration nodes to further match voltages in reset phase. Kickback noise in this comparator is reduced by isolating regeneration nodes of the cross-coupled inverters from the input nodes. Simulated delay of the comparator at ΔVin = 1mV@VDD=1.2V is 69ps. The comparator can operate with a 7GHz clock and a differential input voltage as small as 1mV@VDD=1.2V and can compensate for an input-referred offset of up to 40mV.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); logic gates; noise; transistors; 40mV-input-referred-offset compensation capability; 7GHz-clock 1mV-input-resolution comparator; CMOS process; body voltages; comparator off-set; cross-coupled inverters; frequency 7 GHz; high-speed ADC; input differential triple-well NFET transistor pair; kickback noise; regeneration nodes; reset switch; size 65 nm; voltage 1.2 V; CMOS integrated circuits; CMOS technology; Clocks; Delay; Noise; Switches; Transistors; Comparator; complementary metal-oxide-semiconductor(CMOS); high speed ADC; offset;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering (CCECE), 2011 24th Canadian Conference on

Conference_Location

Niagara Falls, ON

ISSN

0840-7789

Print_ISBN

978-1-4244-9788-1

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2011.6030467

Filename

6030467