DocumentCode
3453283
Title
Implementation of a semi-formal verification for embedded systems
Author
Yun, Zhu ; Xi, Li ; Siyang, Zhao ; Yuchang, Gong
Author_Institution
Dept. of Comput. Sci., Univ. of Sci. & Technol. of China, China
fYear
2005
fDate
16-18 Dec. 2005
Abstract
In the era of billion-transistor design, it is critical to establish effective verification technologies from the system level, all the way down to the implementations. This paper presents a PNPM simulation based verification methodology for equivalence checking between different abstraction levels and property verification at different abstraction levels. How to implement it with coverage-aware input biasing is elaborated.
Keywords
Petri nets; embedded systems; formal verification; pipeline processing; PNPM simulation based verification; Petri net based representation for pipeline modeling; abstraction level; billion-transistor design; coverage-aware input biasing; embedded system; equivalence checking; semiformal verification; Computational modeling; Computer architecture; Computer science; Design methodology; Digital signal processors; Embedded system; Formal verification; Microprocessors; State-space methods; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Software and Systems, 2005. Second International Conference on
Print_ISBN
0-7695-2512-1
Type
conf
DOI
10.1109/ICESS.2005.63
Filename
1609877
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