Title :
Design of an extremely high performance counter mode AES reconfigurable processor
Author :
Fu, Yongzhi ; Hao, Lin ; Zhang, Xuejie ; Yang, Rujin
Author_Institution :
Dept. of Comput. Sci. & Eng., Yunnan Univ., China
Abstract :
In this paper, we presented our implementation of a counter mode AES processor based on the Xilinx Virtex2 FPGA platform. We have studied different techniques to implement the AES rijndael algorithm in reconfigurable hardware and choose the proper method to further optimize the structure of the cipher. This result in a clock frequency of 212.5 mHz and translate to throughput of 27.1 Gb/s, the highest throughput that have ever reported. We also, in this paper, compared the operation modes of AES, their security and efficiency.
Keywords :
cryptography; field programmable gate arrays; logic design; microprocessor chips; 212.5 mHz; 27.1 Gbit/s; AES reconfigurable processor; AES rijndael algorithm; Xilinx Virtexl FPGA platform; advanced encryption standard; reconfigurable hardware; Application specific integrated circuits; Counting circuits; Cryptography; Field programmable gate arrays; Hardware; Optimization methods; Output feedback; Security; Software performance; Throughput;
Conference_Titel :
Embedded Software and Systems, 2005. Second International Conference on
Print_ISBN :
0-7695-2512-1
DOI :
10.1109/ICESS.2005.43
