DocumentCode
3453904
Title
Low-power video decoding system using a reconfigurable processor
Author
Song, Joon Ho ; Lee, Won Chang ; Kim, Doo Hyun ; Kim, Do-Hyung ; Lee, Shihwa
Author_Institution
Samsung Electron., Yongin, South Korea
fYear
2012
fDate
13-16 Jan. 2012
Firstpage
532
Lastpage
533
Abstract
A reconfigurable processor based video decoding system with bistream decoding instruction and memory processing co-processor is presented. Experimental results show that the performance is enhanced about 42% than processor only system. We also estimate that the power consumption is lower than the hardware system about 24% at SD resolution.
Keywords
coprocessors; power consumption; reconfigurable architectures; video coding; SD resolution; bistream decoding instruction; hardware system; low-power video decoding system; memory processing coprocessor; power consumption; reconfigurable processor; Bandwidth; Decoding; Hardware; Memory management; Power demand; SDRAM; VLIW;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ICCE), 2012 IEEE International Conference on
Conference_Location
Las Vegas, NV
ISSN
2158-3994
Print_ISBN
978-1-4577-0230-3
Type
conf
DOI
10.1109/ICCE.2012.6161960
Filename
6161960
Link To Document