Title :
Low-power domino logic multiplier using low-swing technique
Author :
Rjoub, A. ; Koufopavlou, O.
Author_Institution :
VLSI Design Lab., Patras Univ., Greece
Abstract :
A circuit design for a low-power full adder array-based multiplier in domino logic is proposed. It is based on the low-swing voltage technique. The output voltage swing of the domino gate is reduced, resulting in lower power dissipation and improvements in power-delay product. The proposed technique is general and can be used in all domino logic circuit designs. SPICE simulation results have shown that up to 40% power dissipation reduction could be achieved by using the proposed circuit design method
Keywords :
digital arithmetic; logic design; logic gates; low-power electronics; multiplying circuits; circuit design; domino gates; domino logic multiplier; full adder array-based multiplier; low-power multiplier; low-swing technique; power dissipation reduction; power-delay product; Adders; CMOS logic circuits; CMOS technology; Capacitance; Circuit synthesis; Logic arrays; Logic circuits; Logic design; Power dissipation; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.814819
