12-bit hybrid C2C DAC based SAR ADC with floating voltage shield

A successive approximation ADC based on the C2C DAC architecture is introduced. The ADC designed in a 0.18 ¿m CMOS 2 Poly 4 Metal process uses a hybrid capacitive DAC combining the best of the binary weighted capacitive array and the C2C array. C2C ladder based architectures are very attractive for implementation because of its small area, high speed and low power consumption. However a major drawback associated with this DAC is the presence of high parasitic bottom plate capacitances. A concept called the floating voltage shield (FVS) is introduced to reduce the effect of these parasitic capacitances and maximize the effective use of the C2C DAC features. The converter consists of the hybrid DAC, a two stage preamplifier followed by a dynamic latch, switch array and digital circuitry for switching and control. The ADC consumes a maximum power of 630 ¿W at a peak conversion rate of approximately 2MS/s from a 1.8V supply voltage and 40 MHz clock. Use of extremely simple and yet robust analog architectures for the comparator make the ADC operation less prone to process variation errors.