A low power multiphase all-digital phase locked loop with reusing SAR

Author

Chen, Pao-Lung

Author_Institution

Dept. of Comput. & Commun. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol., Kaohsiung, Taiwan

fYear

2010

fDate

21-23 June 2010

Firstpage

695

Lastpage

698

Abstract

This paper presents a low power multiphase all-digital phase locked loop (ADPLL) with reusing successive approximation register (SAR) control. The SAR control unit is reusing both in the coarse and fine stage. The hardware cost and power consumption of reusing SAR control unit is one half of conventional SAR control unit. This output frequency of this multiphase phase locked loop works from 102 MHz to 735 MHz. The power consumption of the proposed low power multiphase ADPLL is 3.6 mW at 320 MHz based on post-layout simulation in TSMC 0.18 μm 1P6M CMOS process. The chip´s core area is 332μm × 187μm.

Keywords

CMOS digital integrated circuits; digital phase locked loops; TSMC CMOS process; frequency 102 MHz to 735 MHz; hardware cost; low power multiphase all-digital phase locked loop; power 3.6 mW; power consumption; size 0.18 mum; successive approximation register control; CMOS process; CMOS technology; Circuit simulation; Clocks; Communication system control; Energy consumption; Filters; Frequency; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Green Circuits and Systems (ICGCS), 2010 International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-6876-8

Electronic_ISBN

978-1-4244-6877-5

Type

conf

DOI

10.1109/ICGCS.2010.5542971

Filename

5542971