Title :
VLSI design of HW/SW interface logic in FC-2
Author :
Jin, Jie ; Cui, Xiaoxin ; Yu, Dunshan
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
In this paper, we propose and compare two architectures of HW/SW interface logic in FC-2, namely as TX/RX scheduler and TX/RX controller. The comparison result shows that the TX/RX controller is more efficient than the TX/RX scheduler. The TX/RX controller is implemented in the proto Fiber Channel (FC) chip fabricated in a 0.18um CMOS technology with six layers of metal. The gate count of TX/RX controller is about 10887 gates and the highest throughput of FC chip is 173MBps. In order to further improve the performance of FC, we propose an improved TX/RX controller based on the implemented one. The two interface logics are thoroughly tested in different test cases and the result shows that the improved one can improve the performance by 2~5 times at the cost of 1.8 times area increased.
Keywords :
VLSI; hardware-software codesign; logic design; microprocessor chips; CMOS technology; FC-2; HW/SW interface logic; TX/RX controller; TX/RX scheduler; VLSI design; fiber channel chip; gate count; size 0.18 mum; Assembly; CMOS logic circuits; CMOS technology; Logic design; Logic testing; Multicast protocols; Open systems; Optical buffering; Random access memory; Very large scale integration;
Conference_Titel :
Green Circuits and Systems (ICGCS), 2010 International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-6876-8
Electronic_ISBN :
978-1-4244-6877-5
DOI :
10.1109/ICGCS.2010.5542972
