VLSI design of HW/SW interface logic in FC-2

In this paper, we propose and compare two architectures of HW/SW interface logic in FC-2, namely as TX/RX scheduler and TX/RX controller. The comparison result shows that the TX/RX controller is more efficient than the TX/RX scheduler. The TX/RX controller is implemented in the proto Fiber Channel (FC) chip fabricated in a 0.18um CMOS technology with six layers of metal. The gate count of TX/RX controller is about 10887 gates and the highest throughput of FC chip is 173MBps. In order to further improve the performance of FC, we propose an improved TX/RX controller based on the implemented one. The two interface logics are thoroughly tested in different test cases and the result shows that the improved one can improve the performance by 2~5 times at the cost of 1.8 times area increased.