Error detection and correction of single event upset (SEU) tolerant latch

Soft errors are a serious concern in state holder circuits at they can cause temporarily malfunctions. C-elements are one of the state holders that are widely used in asynchronous circuits. In this paper, our investigations focus on the vulnerability of different latch types based on C-elements with respect to soft errors. Our aim is to design single event upset (SEU) tolerant latch that has the capability of both detecting and correcting soft errors based on converting single rail to dual-rail configuration and Razor flip flop implementation. In the event of an SEU hitting sensitive nodes and causing the state to temporarily change, an error is generated and a shadow latch restores the correct data. We have demonstrated the functionality of our proposed latch by simulating the design using UMC90nm technology. We also measured error rate of our proposed latch by using an Altera Cyclone II FPGA board. We have obtained the voltage dependence of the error rates. The results show that our proposed latch has less than 1.5% faults propagated at the output.