Title :
SEU-X: A SEu un-excitability prover for SRAM-FPGAs
Author :
Bernardeschi, Cinzia ; Cassano, Luca ; Domenici, Andrea
Author_Institution :
Dept. of Inf. Eng., Univ. of Pisa, Pisa, Italy
Abstract :
We propose an un-excitability prover for Single Event Upset (SEU) faults affecting the configuration memory of logic resources of SRAM-FPGA systems. In particular, we focus on the subset of untestable faults that cannot even be excited, with the aim of optimizing the generation of test patterns, in particular for in-service testing. SEUs in configuration bits of the logic resources actually used by the system are addressed. This makes our fault model much more accurate than the classical stuck-at fault model. The tool relies on the SAL specification language for the modeling of netlists, and on the SAL model checker for the proof of the un-excitability of faults. Results from the application of the tool to some circuits from the ISCAS and ITC benchmarks are reported.
Keywords :
SRAM chips; automatic test pattern generation; field programmable gate arrays; integrated circuit reliability; integrated circuit testing; logic testing; radiation hardening (electronics); ISCAS benchmarks; ITC benchmarks; SAL model checker; SAL specification language; SEU unexcitability prover; SEU-X; SRAM-FPGA systems; configuration memory; fault model; in-service testing; logic resources; netlist modelling; single event upset fault; stuck-at fault model; test pattern generation; Circuit faults; Field programmable gate arrays; Integrated circuit modeling; Multiplexing; Safety; Table lookup; Testing; Model-Checking; SAL; SRAM-FPGA; Single Event Upset; Untestability Proof;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International
Conference_Location :
Sitges
Print_ISBN :
978-1-4673-2082-5
DOI :
10.1109/IOLTS.2012.6313836