Acceleration of pedestrian detection algorithm on novel C2RTL HW/SW Co-design platform

Vehicle-based pedestrian detection systems play a very important role in the field of intelligent transportation. However, existing pedestrian detection algorithms are too computing extensive for traditional vehicle-based processor. Considering the performance and flexibility of hardware/software co-design architecture (CPU+FPGA), it is feasible to implement these algorithms on such platforms. In this paper, we present a popular template-based detection algorithm on such a novel platform which including an ATOM processor and a FPGA-based accelerator, and designed by a novel C2RTL automatic design flow for the platform. Furthermore, we propose performance models for the design and explore configuration parameters of the platform for performance optimization. The experimental results show that our design can achieve nearly 20x speedup for the critical function block compared with the processor-only solution to meet real-time requirement.