An all digital phase-locked loop with modified binary search of frequency acquisition

In this paper, the design of an all digital phase-locked loop is proposed. The phase-lock process is separated into frequency acquisition and phase acquisition that significantly reduces the phase-lock time. By using a modified binary search algorithm, it can accomplish phase lock process within 43 input clock cycles. To generate a high frequency digital clock, a digitally controlled oscillator with 14-bits is used. The DCO frequency range is from 250 MHz to over 500 MHz. The whole chip contains about 5000 transistors and the core chip size is 1.2*1.2 mm²