DocumentCode
3454619
Title
Thermal effects of leakage power in 3D ICs
Author
Ma, Yuchun ; Wang, Kan ; Dong, Sheqin ; Wang, Yu ; Hong, Xianlong
fYear
2010
fDate
21-23 June 2010
Firstpage
578
Lastpage
583
Abstract
Thermal issue is a primary concern in three-dimensional (3D) integrated circuit (IC) design. In modern IC design, leakage power is becoming a key design challenge which contributes to thermal issues. Due to technology scaling, the leakage power is rising so quickly that it largely increases the die temperature. In this paper, we first investigate the impact of leakage power on thermal profile in 3D packings, and then we analyze thermal and leakage aware floorplanning based on 3D-STAF[17] platform. Finally, the effects of thermal controls including the thermal-aware floorplanner and thermal via insertion for thermal management are analyzed in experiment results. The results show that leakage power increases the maximal temperature on the chip greatly about50%. Hence, the required thermal via number also increases greatly about 52.6%.
Keywords
CMOS integrated circuits; integrated circuit design; thermal analysis; thermal management (packaging); 3D IC; 3D packings; 3D-STAF platform; CMOS integrated circuits; die temperature; leakage power; technology scaling; thermal controls; thermal effects; thermal management; thermal-aware fioorplanner; three-dimensional integrated circuit design; CMOS technology; Energy management; Integrated circuit technology; Power generation; Power system management; Temperature; Thermal conductivity; Thermal management; Threshold voltage; Wire; Leakage Power; TSV; Thermal-driven Floorplanning;
fLanguage
English
Publisher
ieee
Conference_Titel
Green Circuits and Systems (ICGCS), 2010 International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-6876-8
Electronic_ISBN
978-1-4244-6877-5
Type
conf
DOI
10.1109/ICGCS.2010.5542995
Filename
5542995
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