Testability of AND-EXOR logic vs. AND-OR logic

Author

Parrilla, L. ; Ortega, J. ; Lloris, A.

Author_Institution

Dept. de Electron. y Tecnologia de Computadores, Granada Univ., Spain

Volume

2

fYear

1998

fDate

1998

Firstpage

213

Abstract

The extensive use of new programmable logic devices as FPGAs in the design of digital systems has motivated a great interest in AND-EXOR logic. The advantages of this logic rest on both the lower number of gates required with respect to the usual AND-OR implementation of digital circuits and the ease of the test pattern generation for some AND-EXOR structures. Nevertheless, no evidence has been presented regarding the advantages of AND-EXOR minimal forms with respect to AND-OR logic in the problem of test generation. The present paper compares the number of test patterns required for testing switching functions which are implemented by AND-OR and AND-EXOR minimal expressions, respectively. Conclusions about the situations in which it is more advantageous to use one or the other logic are established from the analysis of these results

Keywords

circuit testing; design for testability; logic design; logic testing; minimisation; programmable logic devices; AND-EXOR logic; AND-OR logic; FPGA; digital circuits; programmable logic devices; switching functions; test pattern generation; testability; testing; Circuit testing; Digital circuits; Digital systems; Field programmable gate arrays; Logic circuits; Logic design; Logic devices; Logic testing; Programmable logic arrays; Programmable logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.814865

Filename

814865